update edge connector pinout

Fix typo in pinout doc

Electricals/Pinouts/Legacy/front.csv

@@ -1,8 +1,8 @@
 Number,Name,Type,Description,Note
 1,PWRBTN#,I,"Power button, with integrated pull-up",SIO PANSWH#
 3,RSTBTN#,I,"Reset button, with integrated pull-up",SoC SYS_RESET#
-5,SLS_S0,O,"Power statue, output high when S0(Working)",SIO PSON#
+5,SLS_S0,O,"Power status, output high when S0(Working)",SIO PSON#
-7,SLS_S3,O,"Power statue, output high when S0(Working), S3(Sleep)",SoC GPD5
+7,SLS_S3,O,"Power status, output high when S0(Working), S3(Sleep)",SoC GPD5
 9,TSENSE,I,NTC temperature sensor input,SIO TMPIN2
 11,GND,,,
 13,HSIO0_TX+,O,"Differential signal output, coupling capacitor required",

Electricals/Pinouts/README.md

@@ -1,6 +1,6 @@
 # Pinouts
 
-All pin definitions for LattePanda Mu
+All pin definitions for LattePanda Mu(N100/N305 Processor)
 
 ⚠️ Note:  
 Due to the large number of functionally multiplexing pins, you should check the [BIOS functionality documentation](../../Softwares/BIOS/README.md) before starting your design. Do not design directly from the pin definition documentation here.
@@ -114,12 +114,11 @@ Clamshell 22P 0.5mm FFC/FPC Connector
 
 Contacts on eSPI bus for SoC to communicate with SuperIO, can be used to connect diagnostic card (untested).
 
-## SODIMM
+## Edge Connector(DDR4 SODIMM)
 
-DDR4 SODIMM pin table is too long, so I put it in a separate csv file.
+The edge_connector of LattePanda Mu is designed for DDR4 260P SODIMM. But this pin table is too long, so I put it in a separate .xlsx file.
 
-- [Front Side](./front.csv)
+- [LattePanda Mu Edge Connector Pinout](./LattePanda_Mu_Edge_Connector_Pinout.xlsx)
-- [Back Side](./back.csv)
 
 ⚠️ Note:  
 Due to the large number of functionally multiplexing pins, you should check the [BIOS functionality documentation](../../Softwares/BIOS/README.md) before starting your design. Do not design directly from the pin definition documentation here.

Softwares/BIOS/Beta/README.md

@@ -6,10 +6,23 @@ Beta BIOS may contain unforeseen issues and is recommended for professional deve
 
 Modified from **LP-BS-S70NC1R200-SR-A**, with IBECC option enabled for evaluating stability and performance differences.
 
+**Suitable for:** LattePanda Mu N100 8GB
+
 ## LP-BS-S70NC1R200-SR-DEBUG
 
 Enable intel DCI debugging interface and UEFI log output for open source firmware developers
 
+**Suitable for:** LattePanda Mu N100 8GB
+
 ## LP-BS-S70NC1R200-SR-TGPIO
 
 TGPIO function is enabled. A precise 1pps pulse signal is continuously output at Pin 123 for time sensitive applications.
+
+**Suitable for:** LattePanda Mu N100 8GB
+
+## LP-BS-S70NC1R200-DR-B-TGPIO
+
+TGPIO function is enabled. A precise 1pps pulse signal is continuously output at Pin 123 for time sensitive applications.
+
+**Suitable for:** LattePanda Mu N100 16GB / N305 16GB
+

Softwares/BIOS/DFLT/README.md

@@ -1,4 +1,68 @@
-# DEFT Branch
+💡**Note:** The LattePanda Mu compute module is available in 8GB and 16GB memory versions. It is essential to select the correct BIOS firmware as described below.
+
+### For LattePanda Mu N100 **8GB** RAM Model:
+
+- LP-BS-S70NC1R200-SR-B
+- S70NC1R200-8G-A
+
+### For LattePanda Mu N100 / N305 **16GB** RAM Model:
+
+- LP-BS-S70NC1R200-DR-B
+- S70NC1R200-16G-A
+
+---
+
+# BIOS Release Notes
+
+## [2025-12] Latest Release
+**Build Date:** 2025/12/19
+
+### 📂 BIOS Files
+| Variant | Compatible Model | Filename |
+| :--- | :--- | :--- |
+| **PCIe** | LattePanda Mu N100 **8GB** | `S70NC1R200-8G-A.bin` |
+| **PCIe** | LattePanda Mu N100 / N305 **16GB** | `S70NC1R200-16G-A.bin` |
+| **SATA** | LattePanda Mu N100 **8GB** | `S70NC1R200-8G-A-SATA.bin` |
+| **SATA** | LattePanda Mu N100 / N305 **16GB** | `S70NC1R200-16G-A-SATA.bin` |
+
+### 📝 Changelog
+1. Added SMBIOS information.
+2. Added information for eMMC, SATA, NVMe, etc. in the Main tab.
+3. Unlocked PCIe Clock configuration menu.
+4. Unlocked PCIe port ASPM configuration menu (Default: Disabled).
+5. Added toggle options for TP (Touch Panel) and eDP display.
+6. Added GPIO function support and configuration menu.
+7. Enabled SpeedStep(TM) and RC6; changed Package C State Limit to Auto.
+8. Added RTL8111H PXE boot support.
+9. Fixed the issue of duplicate UART numbering in the OS.
+10. Added Windows Recovery support (Requires customized OS).
+
+---
+
+## [2024-06/07] Initial Release
+**Build Date:** 2024/07/08 (PCIe) / 2024/07/05 (SATA)
+
+### 📂 BIOS Files
+- **PCIe**: `LP-BS-S70NC1R200-SR-B.bin`
+
+- **SATA**: `LP-BS-S70NC1R200-SR-B-SATA.bin`
+
+- **Compatible Models**: LattePanda Mu N100 **8GB**
+
+**Build Date:** 2024/06/19 (PCIe) / 2024/06/20 (SATA)
+
+### 📂 BIOS Files
+- **PCIe**: `LP-BS-S70NC1R200-DR-B.bin`
+- **SATA**: `LP-BS-S70NC1R200-DR-B-SATA.bin`
+- **Compatible Models**: LattePanda Mu N100 / N305 **16GB**
+
+
+### 📝 Changelog
+- Initial BIOS firmware release.
+
+---
+
+# DEFT Branch Introduction
 
 Default factory BIOS interface configuration for LattePanda Mu.
 
@@ -42,4 +106,4 @@ Default factory BIOS interface configuration for LattePanda Mu.
 - **GPP_D1**: WWAN_Reset
 - **GPP_D2**: Communication interrupt with Type-C PD controller
 
-Other GPIOs not listed are not allocated specific functions.
+Other GPIOs not listed are not allocated specific functions.

Softwares/BIOS/SATA/README.md

@@ -1,4 +1,69 @@
-# SATA Branch
+
+💡**Note:** The LattePanda Mu compute module is available in 8GB and 16GB memory versions. It is essential to select the correct BIOS firmware as described below.
+
+### For LattePanda Mu N100 **8GB** RAM Model:
+
+- LP-BS-S70NC1R200-SR-B
+- S70NC1R200-8G-A
+
+### For LattePanda Mu N100 / N305 **16GB** RAM Model:
+
+- LP-BS-S70NC1R200-DR-B
+- S70NC1R200-16G-A
+
+---
+
+# BIOS Release Notes
+
+## [2025-12] Latest Release
+**Build Date:** 2025/12/19
+
+### 📂 BIOS Files
+| Variant | Compatible Model | Filename |
+| :--- | :--- | :--- |
+| **PCIe** | LattePanda Mu N100 **8GB** | `S70NC1R200-8G-A.bin` |
+| **PCIe** | LattePanda Mu N100 / N305 **16GB** | `S70NC1R200-16G-A.bin` |
+| **SATA** | LattePanda Mu N100 **8GB** | `S70NC1R200-8G-A-SATA.bin` |
+| **SATA** | LattePanda Mu N100 / N305 **16GB** | `S70NC1R200-16G-A-SATA.bin` |
+
+### 📝 Changelog
+1. Added SMBIOS information.
+2. Added information for eMMC, SATA, NVMe, etc. in the Main tab.
+3. Unlocked PCIe Clock configuration menu.
+4. Unlocked PCIe port ASPM configuration menu (Default: Disabled).
+5. Added toggle options for TP (Touch Panel) and eDP display.
+6. Added GPIO function support and configuration menu.
+7. Enabled SpeedStep(TM) and RC6; changed Package C State Limit to Auto.
+8. Added RTL8111H PXE boot support.
+9. Fixed the issue of duplicate UART numbering in the OS.
+10. Added Windows Recovery support (Requires customized OS).
+
+---
+
+## [2024-06/07] Initial Release
+**Build Date:** 2024/07/08 (PCIe) / 2024/07/05 (SATA)
+
+### 📂 BIOS Files
+- **PCIe**: `LP-BS-S70NC1R200-SR-B.bin`
+
+- **SATA**: `LP-BS-S70NC1R200-SR-B-SATA.bin`
+
+- **Compatible Models**: LattePanda Mu N100 **8GB**
+
+**Build Date:** 2024/06/19 (PCIe) / 2024/06/20 (SATA)
+
+### 📂 BIOS Files
+- **PCIe**: `LP-BS-S70NC1R200-DR-B.bin`
+- **SATA**: `LP-BS-S70NC1R200-DR-B-SATA.bin`
+- **Compatible Models**: LattePanda Mu N100 / N305 **16GB**
+
+
+### 📝 Changelog
+- Initial BIOS firmware release.
+
+---
+
+# SATA Branch Introduction
 
 Enabled integrated SATA controller on the basis of standard BIOS.
 
@@ -15,8 +80,8 @@ Enabled integrated SATA controller on the basis of standard BIOS.
 - **HSIO2**: PCIe 3.0 x1
 - **HSIO3**: PCIe 3.0 x1
 - ==========
-- **HSIO8**: PCIe 3.0 x4 (Lane 0)
+- **HSIO8**: PCIe 3.0 x1
-- **HSIO9**: PCIe 3.0 x4 (Lane 1)
+- **HSIO9**: PCIe 3.0 x1
 - **HSIO10**: SATA 3.0
 - **HSIO11**: SATA 3.0
 - ==========