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2024-04-27 21:21:33 +08:00
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Electricals/Pinouts/README.md Normal file
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# Pinouts
All pin definitions for LattePanda Mu
⚠️ Note:
Due to the large number of functionally multiplexing pins, you should check the [BIOS functionality documentation](../../Softwares/BIOS/README.md) before starting your design. Do not design directly from the pin definition documentation here.
![pinout](./pinout.jpg)
## eDP
I-PEX 20455-040E
| Number | Name | Type | Description |
|--------|-----------|:----:|--------------------------|
| 1 | NC | | |
| 2 | GND | | |
| 3 | DDIA_TX3- | O | Lane 3 (-) |
| 4 | DDIA_TX3+ | O | Lane 3 (+) |
| 5 | GND | | |
| 6 | DDIA_TX2- | O | Lane 2 (-) |
| 7 | DDIA_TX2+ | O | Lane 2 (+) |
| 8 | GND | | |
| 9 | DDIA_TX1- | O | Lane 1 (-) |
| 10 | DDIA_TX1+ | O | Lane 1 (+) |
| 11 | GND | | |
| 12 | DDIA_TX0- | O | Lane 0 (-) |
| 13 | DDIA_TX0+ | O | Lane 0 (+) |
| 14 | GND | | |
| 15 | DDIA_AUX+ | O | Auxiliary channel (+) |
| 16 | DDIA_AUX- | O | Auxiliary channel (-) |
| 17 | GND | | |
| 18 | LCD_VCC | | LCD Power Supplies |
| 19 | LCD_VCC | | LCD Power Supplies |
| 20 | LCD_VCC | | LCD Power Supplies |
| 21 | LCD_VCC | | LCD Power Supplies |
| 22 | Selftest | O | Default Grounding |
| 23 | GND | | |
| 24 | GND | | |
| 25 | GND | | |
| 26 | GND | | |
| 27 | HPD | I | Plug Detection |
| 28 | GND | | |
| 29 | GND | | |
| 30 | GND | | |
| 31 | GND | | |
| 32 | BL_EN | O | Backlight enable |
| 33 | BL_PWM | O | Backlight PWM dimming |
| 34 | NC | | |
| 35 | NC | | |
| 36 | BL_PWR | | Backlight Power Supplies |
| 37 | BL_PWR | | Backlight Power Supplies |
| 38 | BL_PWR | | Backlight Power Supplies |
| 39 | BL_PWR | | Backlight Power Supplies |
| 40 | NC | | |
- **LCD_VCC**: +3.3V
- **BL_PWR**: Same as LattePanda Mu input voltage
- **Selftest**: Factory test pin, ground by default
## Touch
Clamshell 6P 0.5mm FFC/FPC Connector
| Number | Name | Type | Description |
|--------|------------|:----:|-----------------------|
| 1 | I2C0_SCL | O | I2C Bus |
| 2 | I2C0_SDA | I/O | I2C Bus |
| 3 | GND | | |
| 4 | TOUCH_RST# | O | Touch panel reset |
| 5 | TOUCH_INT | I | Touch event interrupt |
| 6 | +3.3V | | Touch panel power |
## MIPI CSI-2
Clamshell 22P 0.5mm FFC/FPC Connector
| Number | Name | Type | Description |
|--------|-----------|:----:|-------------------|
| 1 | GND | | |
| 2 | CSI_B_D0- | I | MIPI Data Lane 0 |
| 3 | CSI_B_D0+ | I | MIPI Data Lane 0 |
| 4 | GND | | |
| 5 | CSI_B_D1- | I | MIPI Data Lane 1 |
| 6 | CSI_B_D1+ | I | MIPI Data Lane 1 |
| 7 | GND | | |
| 8 | CSI_B_CK- | I | MIPI Clock |
| 9 | CSI_B_CK+ | I | MIPI Clock |
| 10 | GND | | |
| 11 | CSI_B_D2- | I | MIPI Data Lane 2 |
| 12 | CSI_B_D2+ | I | MIPI Data Lane 2 |
| 13 | GND | | |
| 14 | CSI_B_D3- | I | MIPI Data Lane 3 |
| 15 | CSI_B_D3+ | I | MIPI Data Lane 3 |
| 16 | GND | | |
| 17 | CAM_RST | O | Camera reset |
| 18 | CAM_MCLK | O | Camera main clock |
| 19 | GND | | |
| 20 | I2C1_SCL | O | I2C bus |
| 21 | I2C1_SDA | I/O | I2C bus |
| 22 | +3.3V | | Camera power |
- **CAM_RST**: SoC GPP_A21
- **CAM_MCLK**: SoC GPP_D4
## SODIMM
DDR4 SODIMM pin table is too long, so I put it in a separate csv file.
- [Front Side](./front.csv)
- [Back Side](./back.csv)
⚠️ Note:
Due to the large number of functionally multiplexing pins, you should check the [BIOS functionality documentation](../../Softwares/BIOS/README.md) before starting your design. Do not design directly from the pin definition documentation here.

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Number,Name,Type,Description
2,FAN1_PWM,O,CPU fan PWM output
4,FAN1_TAC,I,CPU fan tachometer input
6,TAN2_PWM,O,System fan PWM out
8,FAN2_TAC,I,System fan tachometer input
10,SIO_UART_TX,O,SuperIO UART transmitter
12,SIO_UART_RX,I,SuperIO UART receiver
14,GND,,
16,HSIO0_RX+,I,Differential signal input
18,HSIO0_RX-,I,Differential signal input
20,GND,,
22,HSIO1_RX+,I,Differential signal input
24,HSIO1_RX-,I,Differential signal input
26,GND,,
28,HSIO2_RX+,I,Differential signal input
30,HSIO2_RX-,I,Differential signal input
32,GND,,
34,HSIO3_RX+,I,Differential signal input
36,HSIO3_RX-,I,Differential signal input
38,GND,,
40,HSIO8_RX+,I,Differential signal input
42,HSIO8_RX-,I,Differential signal input
44,GND,,
46,HSIO9_RX+,I,Differential signal input
48,HSIO9_RX-,I,Differential signal input
50,GND,,
52,HSIO10_RX+,I,Differential signal input
54,HSIO10_RX-,I,Differential signal input
56,GND,,
58,HSIO11_RX+,I,Differential signal input
60,HSIO11_RX-,I,Differential signal input
62,GND,,
64,HSIO6_RX+,I,Differential signal input
66,HSIO6_RX-,I,Differential signal input
68,GND,,
70,USB2_P4,I/O,USB 2.0 differential signal
72,USB2_N4,I/O,USB 2.0 differential signal
74,GND,,
76,USB2_P7,I/O,USB 2.0 differential signal
78,USB2_N7,I/O,USB 2.0 differential signal
80,GND,,
82,USB2_P8,I/O,USB 2.0 differential signal
84,USB2_N8,I/O,USB 2.0 differential signal
86,GND,,
88,REFCLK3+,O,PCIe reference clock
90,REFCLK3-,O,PCIe reference clock
92,GND,,
94,REFCLK4+,O,PCIe reference clock
96,REFCLK4-,O,PCIe reference clock
98,GND,,
100,PCIECLK_REQ3#,I,REFCLK3 clock request function
102,PCIECLK_REQ4#,I,REFCLK4 clock request function
104,SMB_ALERT#,I,SMBus alert interrupt
106,SMB_CLK,O,SMBus clock
108,SMB_DATA,I/O,SMBus data
110,GND,,
112,USB2_P6,I/O,USB 2.0 differential signal
114,USB2_N6,I/O,USB 2.0 differential signal
116,GND,,
118,GPP_F16,I/O,"GPIO, functions defined by BIOS"
120,GPP_F15,I/O,"GPIO, functions defined by BIOS"
122,GPP_F14,I/O,"GPIO, functions defined by BIOS"
124,GPP_F13,I/O,"GPIO, functions defined by BIOS"
126,GPP_F12,I/O,"GPIO, functions defined by BIOS"
128,GPP_D0,I/O,"GPIO, functions defined by BIOS"
130,GPP_D1,I/O,"GPIO, functions defined by BIOS"
132,GPP_D2,I/O,"GPIO, functions defined by BIOS"
134,GPP_D3,I/O,"GPIO, functions defined by BIOS"
136,GND,,
138,SOC_UART2_TXD,O,SoC UART2 transmitter
140,SOC_UART2_RXD,I,SoC UART2 receiver
142,I2C5_SCL,O,I2C5 clock
144,I2C5_SDA,I/O,I2C5 data
KEY,KEY,KEY,KEY
146,I2C4_SCL,O,I2C4 clock
148,I2C4_SDA,I/O,I2C4 data
150,I2C3_SCL,O,I2C3 clock
152,I2C3_SDA,I/O,I2C3 data
154,I2C2_SCL,O,I2C2 clock
156,I2C2_SDA,I/O,I2C2 data
158,GND,,
160,I2S_MCLK,O,I2S main clock
162,I2S_SCLK,O,I2S bit clock
164,I2S_SFRM,O,I2S word clock
166,I2S_TXD,O,I2S serial data transmitter
168,I2S_RXD,I,I2S serial data receiver
170,GND,,
172,HDA_RST,O,HD Audio reset
174,HDA_BCLK,O,HD Audio bit clock
176,HDA_SYNC,O,HD Audio sync
178,HDA_SDOUT,O,HD Audio serial data out
180,HDA_SDIN,I,HD Audio serial data in
182,GND,,
184,CSI_D_CK+,I,MIPI CSI-2 Port D Clock
186,CSI_D_CK-,I,MIPI CSI-2 Port D Clock
188,GND,,
190,CSI_D_D1+,I,MIPI CSI-2 Port D Data Lane 1
192,CSI_D_D1-,I,MIPI CSI-2 Port D Data Lane 1
194,GND,,
196,CSI_D_D0+,I,MIPI CSI-2 Port D Data Lane 0
198,CSI_D_D0-,I,MIPI CSI-2 Port D Data Lane 0
200,GND,,
202,CSI_C_CK+,I,MIPI CSI-2 Port C Clock
204,CSI_C_CK-,I,MIPI CSI-2 Port C Clock
206,GND,,
208,CSI_C_D1+,I,MIPI CSI-2 Port C Data Lane 1
210,CSI_C_D1-,I,MIPI CSI-2 Port C Data Lane 1
212,GND,,
214,CSI_C_D0+,I,MIPI CSI-2 Port C Data Lane 0
216,CSI_C_D0-,I,MIPI CSI-2 Port C Data Lane 0
218,GND,,
220,TCP1_TXP0,O,TCP1 DP Lane 0/HDMI TMDS Data2
222,TCP1_TXN0,O,TCP1 DP Lane 0/HDMI TMDS Data2
224,GND,,
226,TCP1_TXRXP0,O,TCP1 DP Lane 1/HDMI TMDS Data1
228,TCP1_TXRXN0,O,TCP1 DP Lane 1/HDMI TMDS Data1
230,GND,,
232,TCP1_TXP1,O,TCP1 DP Lane 2/HDMI TMDS Data0
234,TCP1_TXN1,O,TCP1 DP Lane 2/HDMI TMDS Data0
236,GND,,
238,TCP1_TXRXP1,O,TCP1 DP Lane 3/HDMI TMDS Clock
240,TCP1_TXRXN1,O,TCP1 DP Lane 3/HDMI TMDS Clock
242,GND,,
244,TCP1_AUX_P,I/O,TCP1 DP Auxiliary channel
246,TCP1_AUX_N,I/O,TCP1 DP Auxiliary channel
248,GND,,
250,VDC,,Main power input 9~20V
252,VDC,,Main power input 9~20V
254,VDC,,Main power input 9~20V
256,VDC,,Main power input 9~20V
258,VDC,,Main power input 9~20V
260,VDC,,Main power input 9~20V
1 Number Name Type Description
2 2 FAN1_PWM O CPU fan PWM output
3 4 FAN1_TAC I CPU fan tachometer input
4 6 TAN2_PWM O System fan PWM out
5 8 FAN2_TAC I System fan tachometer input
6 10 SIO_UART_TX O SuperIO UART transmitter
7 12 SIO_UART_RX I SuperIO UART receiver
8 14 GND
9 16 HSIO0_RX+ I Differential signal input
10 18 HSIO0_RX- I Differential signal input
11 20 GND
12 22 HSIO1_RX+ I Differential signal input
13 24 HSIO1_RX- I Differential signal input
14 26 GND
15 28 HSIO2_RX+ I Differential signal input
16 30 HSIO2_RX- I Differential signal input
17 32 GND
18 34 HSIO3_RX+ I Differential signal input
19 36 HSIO3_RX- I Differential signal input
20 38 GND
21 40 HSIO8_RX+ I Differential signal input
22 42 HSIO8_RX- I Differential signal input
23 44 GND
24 46 HSIO9_RX+ I Differential signal input
25 48 HSIO9_RX- I Differential signal input
26 50 GND
27 52 HSIO10_RX+ I Differential signal input
28 54 HSIO10_RX- I Differential signal input
29 56 GND
30 58 HSIO11_RX+ I Differential signal input
31 60 HSIO11_RX- I Differential signal input
32 62 GND
33 64 HSIO6_RX+ I Differential signal input
34 66 HSIO6_RX- I Differential signal input
35 68 GND
36 70 USB2_P4 I/O USB 2.0 differential signal
37 72 USB2_N4 I/O USB 2.0 differential signal
38 74 GND
39 76 USB2_P7 I/O USB 2.0 differential signal
40 78 USB2_N7 I/O USB 2.0 differential signal
41 80 GND
42 82 USB2_P8 I/O USB 2.0 differential signal
43 84 USB2_N8 I/O USB 2.0 differential signal
44 86 GND
45 88 REFCLK3+ O PCIe reference clock
46 90 REFCLK3- O PCIe reference clock
47 92 GND
48 94 REFCLK4+ O PCIe reference clock
49 96 REFCLK4- O PCIe reference clock
50 98 GND
51 100 PCIECLK_REQ3# I REFCLK3 clock request function
52 102 PCIECLK_REQ4# I REFCLK4 clock request function
53 104 SMB_ALERT# I SMBus alert interrupt
54 106 SMB_CLK O SMBus clock
55 108 SMB_DATA I/O SMBus data
56 110 GND
57 112 USB2_P6 I/O USB 2.0 differential signal
58 114 USB2_N6 I/O USB 2.0 differential signal
59 116 GND
60 118 GPP_F16 I/O GPIO, functions defined by BIOS
61 120 GPP_F15 I/O GPIO, functions defined by BIOS
62 122 GPP_F14 I/O GPIO, functions defined by BIOS
63 124 GPP_F13 I/O GPIO, functions defined by BIOS
64 126 GPP_F12 I/O GPIO, functions defined by BIOS
65 128 GPP_D0 I/O GPIO, functions defined by BIOS
66 130 GPP_D1 I/O GPIO, functions defined by BIOS
67 132 GPP_D2 I/O GPIO, functions defined by BIOS
68 134 GPP_D3 I/O GPIO, functions defined by BIOS
69 136 GND
70 138 SOC_UART2_TXD O SoC UART2 transmitter
71 140 SOC_UART2_RXD I SoC UART2 receiver
72 142 I2C5_SCL O I2C5 clock
73 144 I2C5_SDA I/O I2C5 data
74 KEY KEY KEY KEY
75 146 I2C4_SCL O I2C4 clock
76 148 I2C4_SDA I/O I2C4 data
77 150 I2C3_SCL O I2C3 clock
78 152 I2C3_SDA I/O I2C3 data
79 154 I2C2_SCL O I2C2 clock
80 156 I2C2_SDA I/O I2C2 data
81 158 GND
82 160 I2S_MCLK O I2S main clock
83 162 I2S_SCLK O I2S bit clock
84 164 I2S_SFRM O I2S word clock
85 166 I2S_TXD O I2S serial data transmitter
86 168 I2S_RXD I I2S serial data receiver
87 170 GND
88 172 HDA_RST O HD Audio reset
89 174 HDA_BCLK O HD Audio bit clock
90 176 HDA_SYNC O HD Audio sync
91 178 HDA_SDOUT O HD Audio serial data out
92 180 HDA_SDIN I HD Audio serial data in
93 182 GND
94 184 CSI_D_CK+ I MIPI CSI-2 Port D Clock
95 186 CSI_D_CK- I MIPI CSI-2 Port D Clock
96 188 GND
97 190 CSI_D_D1+ I MIPI CSI-2 Port D Data Lane 1
98 192 CSI_D_D1- I MIPI CSI-2 Port D Data Lane 1
99 194 GND
100 196 CSI_D_D0+ I MIPI CSI-2 Port D Data Lane 0
101 198 CSI_D_D0- I MIPI CSI-2 Port D Data Lane 0
102 200 GND
103 202 CSI_C_CK+ I MIPI CSI-2 Port C Clock
104 204 CSI_C_CK- I MIPI CSI-2 Port C Clock
105 206 GND
106 208 CSI_C_D1+ I MIPI CSI-2 Port C Data Lane 1
107 210 CSI_C_D1- I MIPI CSI-2 Port C Data Lane 1
108 212 GND
109 214 CSI_C_D0+ I MIPI CSI-2 Port C Data Lane 0
110 216 CSI_C_D0- I MIPI CSI-2 Port C Data Lane 0
111 218 GND
112 220 TCP1_TXP0 O TCP1 DP Lane 0/HDMI TMDS Data2
113 222 TCP1_TXN0 O TCP1 DP Lane 0/HDMI TMDS Data2
114 224 GND
115 226 TCP1_TXRXP0 O TCP1 DP Lane 1/HDMI TMDS Data1
116 228 TCP1_TXRXN0 O TCP1 DP Lane 1/HDMI TMDS Data1
117 230 GND
118 232 TCP1_TXP1 O TCP1 DP Lane 2/HDMI TMDS Data0
119 234 TCP1_TXN1 O TCP1 DP Lane 2/HDMI TMDS Data0
120 236 GND
121 238 TCP1_TXRXP1 O TCP1 DP Lane 3/HDMI TMDS Clock
122 240 TCP1_TXRXN1 O TCP1 DP Lane 3/HDMI TMDS Clock
123 242 GND
124 244 TCP1_AUX_P I/O TCP1 DP Auxiliary channel
125 246 TCP1_AUX_N I/O TCP1 DP Auxiliary channel
126 248 GND
127 250 VDC Main power input 9~20V
128 252 VDC Main power input 9~20V
129 254 VDC Main power input 9~20V
130 256 VDC Main power input 9~20V
131 258 VDC Main power input 9~20V
132 260 VDC Main power input 9~20V

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Number,Name,Type,Description
1,PWRBTN#,I,"Power button, with integrated pull-up"
3,RSTBTN#,I,"Reset button, with integrated pull-up"
5,SLS_S0,O,"Power statue, output high when S0(Working)"
7,SLS_S3,O,"Power statue, output high when S0(Working), S3(Sleep)"
9,TSENSE,I,NTC temperature sensor input
11,GND,,
13,HSIO0_TX+,O,"Differential signal output, coupling capacitor required"
15,HSIO0_TX-,O,"Differential signal output, coupling capacitor required"
17,GND,,
19,HSIO1_TX+,O,"Differential signal output, coupling capacitor required"
21,HSIO1_TX-,O,"Differential signal output, coupling capacitor required"
23,GND,,
25,HSIO2_TX+,O,"Differential signal output, coupling capacitor required"
27,HSIO2_TX-,O,"Differential signal output, coupling capacitor required"
29,GND,,
31,HSIO3_TX+,O,"Differential signal output, coupling capacitor required"
33,HSIO3_TX-,O,"Differential signal output, coupling capacitor required"
35,GND,,
37,HSIO8_TX+,O,"Differential signal output, coupling capacitor required"
39,HSIO8_TX-,O,"Differential signal output, coupling capacitor required"
41,GND,,
43,HSIO9_TX+,O,"Differential signal output, coupling capacitor required"
45,HSIO9_TX-,O,"Differential signal output, coupling capacitor required"
47,GND,,
49,HSIO10_TX+,O,"Differential signal output, coupling capacitor required"
51,HSIO10_TX-,O,"Differential signal output, coupling capacitor required"
53,GND,,
55,HSIO11_TX+,O,"Differential signal output, coupling capacitor required"
57,HSIO11_TX-,O,"Differential signal output, coupling capacitor required"
59,GND,,
61,HSIO6_TX+,O,"Differential signal output, coupling capacitor required"
63,HSIO6_TX-,O,"Differential signal output, coupling capacitor required"
65,GND,,
67,USB2_P1-,I/O,USB 2.0 differential signal
69,USB2_P1+,I/O,USB 2.0 differential signal
71,GND,,
73,USB2_P2-,I/O,USB 2.0 differential signal
75,USB2_P2+,I/O,USB 2.0 differential signal
77,GND,,
79,USB2_P3-,I/O,USB 2.0 differential signal
81,USB2_P3+,I/O,USB 2.0 differential signal
83,GND,,
85,REFCLK0+,O,PCIe reference clock
87,REFCLK0-,O,PCIe reference clock
89,GND,,
91,REFCLK1+,O,PCIe reference clock
93,REFCLK1-,O,PCIe reference clock
95,GND,,
97,REFCLK2+,O,PCIe reference clock
99,REFCLK2-,O,PCIe reference clock
101,GND,,
103,WAKE#,I,Wake Mu when pull-down
105,PLTRST#,O,Platform reset signal
107,GND,,
109,USB2_P5-,I/O,USB 2.0 differential signal
111,USB2_P5+,I/O,USB 2.0 differential signal
113,GND,,
115,VBAT,,RTC battery input
117,PROCHOT#,I,Overheat protect when pull-down
119,GPP_E0,I/O,"GPIO, functions defined by BIOS"
121,GPP_A12,I/O,"GPIO, functions defined by BIOS"
123,GPP_B14,I/O,"GPIO, functions defined by BIOS"
125,GPP_B11,I/O,"GPIO, functions defined by BIOS"
127,TPM_IRQ,I,discrete TPM interrupt
129,USB_OC#,I,USB over current signal
131,SUSCLK,O,32.768kHz clock output
133,BIOS_SEL#,I,BIOS select: pull-up: integrated ROM; pull-down: carrier ROM
135,GND,,
137,UART0_RXD,I,SoC UART0 receiver
139,UART0_TXD,O,SoC UART0 transmitter
141,UART1_RXD,I,SoC UART1 receiver
143,UART1_TXD,O,SoC UART1 transmitter
KEY,KEY,KEY,KEY
145,SML1_DATA,I/O,SMLink1 data
147,SML1_CLK,O,SMLink1 clock
149,SML1_ALERT#,I,SMLink1 alert
151,GND,,
153,SPI_IO3,I/O,"SPI interface, BIOS and dTPM specific"
155,SPI_CLK,O,"SPI interface, BIOS and dTPM specific"
157,SPI_CS2#,O,"SPI chip select, dTPM specific"
159,SPI_MOSI/SPI_IO0,I/O,"SPI interface, BIOS and dTPM specific"
161,SPI_IO2,I/O,"SPI interface, BIOS and dTPM specific"
163,SPI_MISO/SPI_IO1,I/O,"SPI interface, BIOS and dTPM specific"
165,SPI_CS#,O,"SPI chip select, BIOS ROM specific"
167,GND,,
169,DDIB_DDC_SDA,I/O,DDIB HDMI display data channel data
171,DDIB_DDC_SCL,O,DDIB HDMI display data channel clock
173,TCP1_DDC_SDA,I/O,TCP1 HDMI display data channel data
175,TCP1_DDC_SCL,O,TCP1 HDMI display data channel clock
177,TCP0_DDC_SDA,I/O,TCP0 HDMI display data channel data
179,TCP0_DDC_SCL,O,TCP0 HDMI display data channel clock
181,GND,,
183,DDIB_HPD,I,DDIB hot plug detect
185,TCP1_HPD,I,TCP1 hot plug detect
187,TCP0_HPD,I,TCP0 hot plug detect
189,GND,,
191,DDIB_AUX-,I/O,DDIB DP Auxiliary channel
193,DDIB_AUX+,I/O,DDIB DP Auxiliary channel
195,GND,,
197,DDIB_TX3-,O,DDIB DP Lane 3/HDMI TMDS Clock
199,DDIB_TX3+,O,DDIB DP Lane 3/HDMI TMDS Clock
201,GND,,
203,DDIB_TX2-,O,DDIB DP Lane 2/HDMI TMDS Data0
205,DDIB_TX2+,O,DDIB DP Lane 2/HDMI TMDS Data0
207,GND,,
209,DDIB_TX1-,O,DDIB DP Lane 1/HDMI TMDS Data1
211,DDIB_TX1+,O,DDIB DP Lane 1/HDMI TMDS Data1
213,GND,,
215,DDIB_TX0-,O,DDIB DP Lane 0/HDMI TMDS Data2
217,DDIB_TX0+,O,DDIB DP Lane 0/HDMI TMDS Data2
219,GND,,
221,TCP0_AUX-,I/O,TCP0 DP Auxiliary channel
223,TCP0_AUX+,I/O,TCP0 DP Auxiliary channel
225,GND,,
227,TCP0_TXRX1-,O,TCP0 DP Lane 3/HDMI TMDS Clock
229,TCP0_TXRX1+,O,TCP0 DP Lane 3/HDMI TMDS Clock
231,GND,,
233,TCP0_TX1-,O,TCP0 DP Lane 2/HDMI TMDS Data0
235,TCP0_TX1+,O,TCP0 DP Lane 2/HDMI TMDS Data0
237,GND,,
239,TCP0_TXRX0-,O,TCP0 DP Lane 1/HDMI TMDS Data1
241,TCP0_TXRX0+,O,TCP0 DP Lane 1/HDMI TMDS Data1
243,GND,,
245,TCP0_TX0-,O,TCP0 DP Lane 0/HDMI TMDS Data2
247,TCP0_TX0+,O,TCP0 DP Lane 0/HDMI TMDS Data2
249,GND,,
251,VIN,,Main power input 9~20V
253,VIN,,Main power input 9~20V
255,VIN,,Main power input 9~20V
257,VIN,,Main power input 9~20V
259,VIN,,Main power input 9~20V
1 Number Name Type Description
2 1 PWRBTN# I Power button, with integrated pull-up
3 3 RSTBTN# I Reset button, with integrated pull-up
4 5 SLS_S0 O Power statue, output high when S0(Working)
5 7 SLS_S3 O Power statue, output high when S0(Working), S3(Sleep)
6 9 TSENSE I NTC temperature sensor input
7 11 GND
8 13 HSIO0_TX+ O Differential signal output, coupling capacitor required
9 15 HSIO0_TX- O Differential signal output, coupling capacitor required
10 17 GND
11 19 HSIO1_TX+ O Differential signal output, coupling capacitor required
12 21 HSIO1_TX- O Differential signal output, coupling capacitor required
13 23 GND
14 25 HSIO2_TX+ O Differential signal output, coupling capacitor required
15 27 HSIO2_TX- O Differential signal output, coupling capacitor required
16 29 GND
17 31 HSIO3_TX+ O Differential signal output, coupling capacitor required
18 33 HSIO3_TX- O Differential signal output, coupling capacitor required
19 35 GND
20 37 HSIO8_TX+ O Differential signal output, coupling capacitor required
21 39 HSIO8_TX- O Differential signal output, coupling capacitor required
22 41 GND
23 43 HSIO9_TX+ O Differential signal output, coupling capacitor required
24 45 HSIO9_TX- O Differential signal output, coupling capacitor required
25 47 GND
26 49 HSIO10_TX+ O Differential signal output, coupling capacitor required
27 51 HSIO10_TX- O Differential signal output, coupling capacitor required
28 53 GND
29 55 HSIO11_TX+ O Differential signal output, coupling capacitor required
30 57 HSIO11_TX- O Differential signal output, coupling capacitor required
31 59 GND
32 61 HSIO6_TX+ O Differential signal output, coupling capacitor required
33 63 HSIO6_TX- O Differential signal output, coupling capacitor required
34 65 GND
35 67 USB2_P1- I/O USB 2.0 differential signal
36 69 USB2_P1+ I/O USB 2.0 differential signal
37 71 GND
38 73 USB2_P2- I/O USB 2.0 differential signal
39 75 USB2_P2+ I/O USB 2.0 differential signal
40 77 GND
41 79 USB2_P3- I/O USB 2.0 differential signal
42 81 USB2_P3+ I/O USB 2.0 differential signal
43 83 GND
44 85 REFCLK0+ O PCIe reference clock
45 87 REFCLK0- O PCIe reference clock
46 89 GND
47 91 REFCLK1+ O PCIe reference clock
48 93 REFCLK1- O PCIe reference clock
49 95 GND
50 97 REFCLK2+ O PCIe reference clock
51 99 REFCLK2- O PCIe reference clock
52 101 GND
53 103 WAKE# I Wake Mu when pull-down
54 105 PLTRST# O Platform reset signal
55 107 GND
56 109 USB2_P5- I/O USB 2.0 differential signal
57 111 USB2_P5+ I/O USB 2.0 differential signal
58 113 GND
59 115 VBAT RTC battery input
60 117 PROCHOT# I Overheat protect when pull-down
61 119 GPP_E0 I/O GPIO, functions defined by BIOS
62 121 GPP_A12 I/O GPIO, functions defined by BIOS
63 123 GPP_B14 I/O GPIO, functions defined by BIOS
64 125 GPP_B11 I/O GPIO, functions defined by BIOS
65 127 TPM_IRQ I discrete TPM interrupt
66 129 USB_OC# I USB over current signal
67 131 SUSCLK O 32.768kHz clock output
68 133 BIOS_SEL# I BIOS select: pull-up: integrated ROM; pull-down: carrier ROM
69 135 GND
70 137 UART0_RXD I SoC UART0 receiver
71 139 UART0_TXD O SoC UART0 transmitter
72 141 UART1_RXD I SoC UART1 receiver
73 143 UART1_TXD O SoC UART1 transmitter
74 KEY KEY KEY KEY
75 145 SML1_DATA I/O SMLink1 data
76 147 SML1_CLK O SMLink1 clock
77 149 SML1_ALERT# I SMLink1 alert
78 151 GND
79 153 SPI_IO3 I/O SPI interface, BIOS and dTPM specific
80 155 SPI_CLK O SPI interface, BIOS and dTPM specific
81 157 SPI_CS2# O SPI chip select, dTPM specific
82 159 SPI_MOSI/SPI_IO0 I/O SPI interface, BIOS and dTPM specific
83 161 SPI_IO2 I/O SPI interface, BIOS and dTPM specific
84 163 SPI_MISO/SPI_IO1 I/O SPI interface, BIOS and dTPM specific
85 165 SPI_CS# O SPI chip select, BIOS ROM specific
86 167 GND
87 169 DDIB_DDC_SDA I/O DDIB HDMI display data channel data
88 171 DDIB_DDC_SCL O DDIB HDMI display data channel clock
89 173 TCP1_DDC_SDA I/O TCP1 HDMI display data channel data
90 175 TCP1_DDC_SCL O TCP1 HDMI display data channel clock
91 177 TCP0_DDC_SDA I/O TCP0 HDMI display data channel data
92 179 TCP0_DDC_SCL O TCP0 HDMI display data channel clock
93 181 GND
94 183 DDIB_HPD I DDIB hot plug detect
95 185 TCP1_HPD I TCP1 hot plug detect
96 187 TCP0_HPD I TCP0 hot plug detect
97 189 GND
98 191 DDIB_AUX- I/O DDIB DP Auxiliary channel
99 193 DDIB_AUX+ I/O DDIB DP Auxiliary channel
100 195 GND
101 197 DDIB_TX3- O DDIB DP Lane 3/HDMI TMDS Clock
102 199 DDIB_TX3+ O DDIB DP Lane 3/HDMI TMDS Clock
103 201 GND
104 203 DDIB_TX2- O DDIB DP Lane 2/HDMI TMDS Data0
105 205 DDIB_TX2+ O DDIB DP Lane 2/HDMI TMDS Data0
106 207 GND
107 209 DDIB_TX1- O DDIB DP Lane 1/HDMI TMDS Data1
108 211 DDIB_TX1+ O DDIB DP Lane 1/HDMI TMDS Data1
109 213 GND
110 215 DDIB_TX0- O DDIB DP Lane 0/HDMI TMDS Data2
111 217 DDIB_TX0+ O DDIB DP Lane 0/HDMI TMDS Data2
112 219 GND
113 221 TCP0_AUX- I/O TCP0 DP Auxiliary channel
114 223 TCP0_AUX+ I/O TCP0 DP Auxiliary channel
115 225 GND
116 227 TCP0_TXRX1- O TCP0 DP Lane 3/HDMI TMDS Clock
117 229 TCP0_TXRX1+ O TCP0 DP Lane 3/HDMI TMDS Clock
118 231 GND
119 233 TCP0_TX1- O TCP0 DP Lane 2/HDMI TMDS Data0
120 235 TCP0_TX1+ O TCP0 DP Lane 2/HDMI TMDS Data0
121 237 GND
122 239 TCP0_TXRX0- O TCP0 DP Lane 1/HDMI TMDS Data1
123 241 TCP0_TXRX0+ O TCP0 DP Lane 1/HDMI TMDS Data1
124 243 GND
125 245 TCP0_TX0- O TCP0 DP Lane 0/HDMI TMDS Data2
126 247 TCP0_TX0+ O TCP0 DP Lane 0/HDMI TMDS Data2
127 249 GND
128 251 VIN Main power input 9~20V
129 253 VIN Main power input 9~20V
130 255 VIN Main power input 9~20V
131 257 VIN Main power input 9~20V
132 259 VIN Main power input 9~20V

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Electricals/README.md
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@@ -5,3 +5,5 @@
- Examples: Sample projects
- Libraries: Symbol and footprint libraries for LattePanda Mu
- Pinouts: All pin definitions for LattePanda Mu