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update edge connector pinout

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yuyouliang
2026-01-14 12:23:13 +08:00
parent 7a42eed521
commit 73acf69647
4 changed files with 4 additions and 5 deletions
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132
Electricals/Pinouts/Legacy/front.csv Normal file
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Number,Name,Type,Description,Note
1,PWRBTN#,I,"Power button, with integrated pull-up",SIO PANSWH#
3,RSTBTN#,I,"Reset button, with integrated pull-up",SoC SYS_RESET#
5,SLS_S0,O,"Power status, output high when S0(Working)",SIO PSON#
7,SLS_S3,O,"Power status, output high when S0(Working), S3(Sleep)",SoC GPD5
9,TSENSE,I,NTC temperature sensor input,SIO TMPIN2
11,GND,,,
13,HSIO0_TX+,O,"Differential signal output, coupling capacitor required",
15,HSIO0_TX-,O,"Differential signal output, coupling capacitor required",
17,GND,,,
19,HSIO1_TX+,O,"Differential signal output, coupling capacitor required",
21,HSIO1_TX-,O,"Differential signal output, coupling capacitor required",
23,GND,,,
25,HSIO2_TX+,O,"Differential signal output, coupling capacitor required",
27,HSIO2_TX-,O,"Differential signal output, coupling capacitor required",
29,GND,,,
31,HSIO3_TX+,O,"Differential signal output, coupling capacitor required",
33,HSIO3_TX-,O,"Differential signal output, coupling capacitor required",
35,GND,,,
37,HSIO8_TX+,O,"Differential signal output, coupling capacitor required",
39,HSIO8_TX-,O,"Differential signal output, coupling capacitor required",
41,GND,,,
43,HSIO9_TX+,O,"Differential signal output, coupling capacitor required",
45,HSIO9_TX-,O,"Differential signal output, coupling capacitor required",
47,GND,,,
49,HSIO10_TX+,O,"Differential signal output, coupling capacitor required",
51,HSIO10_TX-,O,"Differential signal output, coupling capacitor required",
53,GND,,,
55,HSIO11_TX+,O,"Differential signal output, coupling capacitor required",
57,HSIO11_TX-,O,"Differential signal output, coupling capacitor required",
59,GND,,,
61,HSIO6_TX+,O,"Differential signal output, coupling capacitor required",
63,HSIO6_TX-,O,"Differential signal output, coupling capacitor required",
65,GND,,,
67,USB2_P1-,I/O,USB 2.0 differential signal,
69,USB2_P1+,I/O,USB 2.0 differential signal,
71,GND,,,
73,USB2_P2-,I/O,USB 2.0 differential signal,
75,USB2_P2+,I/O,USB 2.0 differential signal,
77,GND,,,
79,USB2_P3-,I/O,USB 2.0 differential signal,
81,USB2_P3+,I/O,USB 2.0 differential signal,
83,GND,,,
85,REFCLK0+,O,PCIe reference clock,
87,REFCLK0-,O,PCIe reference clock,
89,GND,,,
91,REFCLK1+,O,PCIe reference clock,
93,REFCLK1-,O,PCIe reference clock,
95,GND,,,
97,REFCLK2+,O,PCIe reference clock,
99,REFCLK2-,O,PCIe reference clock,
101,GND,,,
103,WAKE#,I,Wake Mu when pull-down,SoC WAKE#
105,PLTRST#,O,Platform reset signal,SoC GPP_B13
107,GND,,,
109,USB2_P5-,I/O,USB 2.0 differential signal,
111,USB2_P5+,I/O,USB 2.0 differential signal,
113,GND,,,
115,VBAT,,RTC battery input,SoC VCCRTC
117,PROCHOT#,I,Overheat protect when pull-down,SoC PROCHOT#
119,GPP_E0,I/O,"GPIO, functions defined by BIOS",
121,GPP_A12,I/O,"GPIO, functions defined by BIOS",
123,GPP_B14,I/O,"GPIO, functions defined by BIOS",
125,GPP_B11,I/O,"GPIO, functions defined by BIOS",
127,TPM_IRQ,I,discrete TPM interrupt,SoC GPP_B4
129,USB_OC#,I,USB over current signal,SoC GPP_A16
131,SUSCLK,O,32.768kHz clock output,SoC GPD8
133,BIOS_SEL#,I,BIOS select: pull-up: integrated ROM; pull-down: carrier ROM,
135,GND,,,
137,UART0_RXD,I,SoC UART0 receiver ,SoC GPP_H10
139,UART0_TXD,O,SoC UART0 transmitter ,SoC GPP_H11
141,UART1_RXD,I,SoC UART1 receiver ,SoC GPP_D17
143,UART1_TXD,O,SoC UART1 transmitter ,SoC GPP_D18
KEY,KEY,KEY,KEY,
145,SML1_DATA,I/O,SMLink1 data,SoC GPP_C7
147,SML1_CLK,O,SMLink1 clock,SoC GPP_C6
149,SML1_ALERT#,I,SMLink1 alert,SoC GPP_B23
151,GND,,,
153,SPI_IO3,I/O,"SPI interface, BIOS and dTPM specific",
155,SPI_CLK,O,"SPI interface, BIOS and dTPM specific",
157,SPI_CS2#,O,"SPI chip select, dTPM specific",
159,SPI_MOSI/SPI_IO0,I/O,"SPI interface, BIOS and dTPM specific",
161,SPI_IO2,I/O,"SPI interface, BIOS and dTPM specific",
163,SPI_MISO/SPI_IO1,I/O,"SPI interface, BIOS and dTPM specific",
165,SPI_CS#,O,"SPI chip select, BIOS ROM specific",
167,GND,,,
169,DDIB_DDC_SDA,I/O,DDIB HDMI display data channel data,SoC GPP_H17
171,DDIB_DDC_SCL,O,DDIB HDMI display data channel clock,SoC GPP_H15
173,TCP1_DDC_SDA,I/O,TCP1 HDMI display data channel data,SoC GPP_E21
175,TCP1_DDC_SCL,O,TCP1 HDMI display data channel clock,SoC GPP_E20
177,TCP0_DDC_SDA,I/O,TCP0 HDMI display data channel data,SoC GPP_E19
179,TCP0_DDC_SCL,O,TCP0 HDMI display data channel clock,SoC GPP_E18
181,GND,,,
183,DDIB_HPD,I,DDIB hot plug detect,SoC GPP_A18
185,TCP1_HPD,I,TCP1 hot plug detect,SoC GPP_A20
187,TCP0_HPD,I,TCP0 hot plug detect,SoC GPP_A19
189,GND,,,
191,DDIB_AUX-,I/O,DDIB DP Auxiliary channel,
193,DDIB_AUX+,I/O,DDIB DP Auxiliary channel,
195,GND,,,
197,DDIB_TX3-,O,DDIB DP Lane 3/HDMI TMDS Clock,
199,DDIB_TX3+,O,DDIB DP Lane 3/HDMI TMDS Clock,
201,GND,,,
203,DDIB_TX2-,O,DDIB DP Lane 2/HDMI TMDS Data0,
205,DDIB_TX2+,O,DDIB DP Lane 2/HDMI TMDS Data0,
207,GND,,,
209,DDIB_TX1-,O,DDIB DP Lane 1/HDMI TMDS Data1,
211,DDIB_TX1+,O,DDIB DP Lane 1/HDMI TMDS Data1,
213,GND,,,
215,DDIB_TX0-,O,DDIB DP Lane 0/HDMI TMDS Data2,
217,DDIB_TX0+,O,DDIB DP Lane 0/HDMI TMDS Data2,
219,GND,,,
221,TCP0_AUX-,I/O,TCP0 DP Auxiliary channel,
223,TCP0_AUX+,I/O,TCP0 DP Auxiliary channel,
225,GND,,,
227,TCP0_TXRX1-,O,TCP0 DP Lane 3/HDMI TMDS Clock,
229,TCP0_TXRX1+,O,TCP0 DP Lane 3/HDMI TMDS Clock,
231,GND,,,
233,TCP0_TX1-,O,TCP0 DP Lane 2/HDMI TMDS Data0,
235,TCP0_TX1+,O,TCP0 DP Lane 2/HDMI TMDS Data0,
237,GND,,,
239,TCP0_TXRX0-,O,TCP0 DP Lane 1/HDMI TMDS Data1,
241,TCP0_TXRX0+,O,TCP0 DP Lane 1/HDMI TMDS Data1,
243,GND,,,
245,TCP0_TX0-,O,TCP0 DP Lane 0/HDMI TMDS Data2,
247,TCP0_TX0+,O,TCP0 DP Lane 0/HDMI TMDS Data2,
249,GND,,,
251,VIN,,Main power input 9~20V,
253,VIN,,Main power input 9~20V,
255,VIN,,Main power input 9~20V,
257,VIN,,Main power input 9~20V,
259,VIN,,Main power input 9~20V,
1 Number Name Type Description Note
2 1 PWRBTN# I Power button, with integrated pull-up SIO PANSWH#
3 3 RSTBTN# I Reset button, with integrated pull-up SoC SYS_RESET#
4 5 SLS_S0 O Power status, output high when S0(Working) SIO PSON#
5 7 SLS_S3 O Power status, output high when S0(Working), S3(Sleep) SoC GPD5
6 9 TSENSE I NTC temperature sensor input SIO TMPIN2
7 11 GND
8 13 HSIO0_TX+ O Differential signal output, coupling capacitor required
9 15 HSIO0_TX- O Differential signal output, coupling capacitor required
10 17 GND
11 19 HSIO1_TX+ O Differential signal output, coupling capacitor required
12 21 HSIO1_TX- O Differential signal output, coupling capacitor required
13 23 GND
14 25 HSIO2_TX+ O Differential signal output, coupling capacitor required
15 27 HSIO2_TX- O Differential signal output, coupling capacitor required
16 29 GND
17 31 HSIO3_TX+ O Differential signal output, coupling capacitor required
18 33 HSIO3_TX- O Differential signal output, coupling capacitor required
19 35 GND
20 37 HSIO8_TX+ O Differential signal output, coupling capacitor required
21 39 HSIO8_TX- O Differential signal output, coupling capacitor required
22 41 GND
23 43 HSIO9_TX+ O Differential signal output, coupling capacitor required
24 45 HSIO9_TX- O Differential signal output, coupling capacitor required
25 47 GND
26 49 HSIO10_TX+ O Differential signal output, coupling capacitor required
27 51 HSIO10_TX- O Differential signal output, coupling capacitor required
28 53 GND
29 55 HSIO11_TX+ O Differential signal output, coupling capacitor required
30 57 HSIO11_TX- O Differential signal output, coupling capacitor required
31 59 GND
32 61 HSIO6_TX+ O Differential signal output, coupling capacitor required
33 63 HSIO6_TX- O Differential signal output, coupling capacitor required
34 65 GND
35 67 USB2_P1- I/O USB 2.0 differential signal
36 69 USB2_P1+ I/O USB 2.0 differential signal
37 71 GND
38 73 USB2_P2- I/O USB 2.0 differential signal
39 75 USB2_P2+ I/O USB 2.0 differential signal
40 77 GND
41 79 USB2_P3- I/O USB 2.0 differential signal
42 81 USB2_P3+ I/O USB 2.0 differential signal
43 83 GND
44 85 REFCLK0+ O PCIe reference clock
45 87 REFCLK0- O PCIe reference clock
46 89 GND
47 91 REFCLK1+ O PCIe reference clock
48 93 REFCLK1- O PCIe reference clock
49 95 GND
50 97 REFCLK2+ O PCIe reference clock
51 99 REFCLK2- O PCIe reference clock
52 101 GND
53 103 WAKE# I Wake Mu when pull-down SoC WAKE#
54 105 PLTRST# O Platform reset signal SoC GPP_B13
55 107 GND
56 109 USB2_P5- I/O USB 2.0 differential signal
57 111 USB2_P5+ I/O USB 2.0 differential signal
58 113 GND
59 115 VBAT RTC battery input SoC VCCRTC
60 117 PROCHOT# I Overheat protect when pull-down SoC PROCHOT#
61 119 GPP_E0 I/O GPIO, functions defined by BIOS
62 121 GPP_A12 I/O GPIO, functions defined by BIOS
63 123 GPP_B14 I/O GPIO, functions defined by BIOS
64 125 GPP_B11 I/O GPIO, functions defined by BIOS
65 127 TPM_IRQ I discrete TPM interrupt SoC GPP_B4
66 129 USB_OC# I USB over current signal SoC GPP_A16
67 131 SUSCLK O 32.768kHz clock output SoC GPD8
68 133 BIOS_SEL# I BIOS select: pull-up: integrated ROM; pull-down: carrier ROM
69 135 GND
70 137 UART0_RXD I SoC UART0 receiver SoC GPP_H10
71 139 UART0_TXD O SoC UART0 transmitter SoC GPP_H11
72 141 UART1_RXD I SoC UART1 receiver SoC GPP_D17
73 143 UART1_TXD O SoC UART1 transmitter SoC GPP_D18
74 KEY KEY KEY KEY
75 145 SML1_DATA I/O SMLink1 data SoC GPP_C7
76 147 SML1_CLK O SMLink1 clock SoC GPP_C6
77 149 SML1_ALERT# I SMLink1 alert SoC GPP_B23
78 151 GND
79 153 SPI_IO3 I/O SPI interface, BIOS and dTPM specific
80 155 SPI_CLK O SPI interface, BIOS and dTPM specific
81 157 SPI_CS2# O SPI chip select, dTPM specific
82 159 SPI_MOSI/SPI_IO0 I/O SPI interface, BIOS and dTPM specific
83 161 SPI_IO2 I/O SPI interface, BIOS and dTPM specific
84 163 SPI_MISO/SPI_IO1 I/O SPI interface, BIOS and dTPM specific
85 165 SPI_CS# O SPI chip select, BIOS ROM specific
86 167 GND
87 169 DDIB_DDC_SDA I/O DDIB HDMI display data channel data SoC GPP_H17
88 171 DDIB_DDC_SCL O DDIB HDMI display data channel clock SoC GPP_H15
89 173 TCP1_DDC_SDA I/O TCP1 HDMI display data channel data SoC GPP_E21
90 175 TCP1_DDC_SCL O TCP1 HDMI display data channel clock SoC GPP_E20
91 177 TCP0_DDC_SDA I/O TCP0 HDMI display data channel data SoC GPP_E19
92 179 TCP0_DDC_SCL O TCP0 HDMI display data channel clock SoC GPP_E18
93 181 GND
94 183 DDIB_HPD I DDIB hot plug detect SoC GPP_A18
95 185 TCP1_HPD I TCP1 hot plug detect SoC GPP_A20
96 187 TCP0_HPD I TCP0 hot plug detect SoC GPP_A19
97 189 GND
98 191 DDIB_AUX- I/O DDIB DP Auxiliary channel
99 193 DDIB_AUX+ I/O DDIB DP Auxiliary channel
100 195 GND
101 197 DDIB_TX3- O DDIB DP Lane 3/HDMI TMDS Clock
102 199 DDIB_TX3+ O DDIB DP Lane 3/HDMI TMDS Clock
103 201 GND
104 203 DDIB_TX2- O DDIB DP Lane 2/HDMI TMDS Data0
105 205 DDIB_TX2+ O DDIB DP Lane 2/HDMI TMDS Data0
106 207 GND
107 209 DDIB_TX1- O DDIB DP Lane 1/HDMI TMDS Data1
108 211 DDIB_TX1+ O DDIB DP Lane 1/HDMI TMDS Data1
109 213 GND
110 215 DDIB_TX0- O DDIB DP Lane 0/HDMI TMDS Data2
111 217 DDIB_TX0+ O DDIB DP Lane 0/HDMI TMDS Data2
112 219 GND
113 221 TCP0_AUX- I/O TCP0 DP Auxiliary channel
114 223 TCP0_AUX+ I/O TCP0 DP Auxiliary channel
115 225 GND
116 227 TCP0_TXRX1- O TCP0 DP Lane 3/HDMI TMDS Clock
117 229 TCP0_TXRX1+ O TCP0 DP Lane 3/HDMI TMDS Clock
118 231 GND
119 233 TCP0_TX1- O TCP0 DP Lane 2/HDMI TMDS Data0
120 235 TCP0_TX1+ O TCP0 DP Lane 2/HDMI TMDS Data0
121 237 GND
122 239 TCP0_TXRX0- O TCP0 DP Lane 1/HDMI TMDS Data1
123 241 TCP0_TXRX0+ O TCP0 DP Lane 1/HDMI TMDS Data1
124 243 GND
125 245 TCP0_TX0- O TCP0 DP Lane 0/HDMI TMDS Data2
126 247 TCP0_TX0+ O TCP0 DP Lane 0/HDMI TMDS Data2
127 249 GND
128 251 VIN Main power input 9~20V
129 253 VIN Main power input 9~20V
130 255 VIN Main power input 9~20V
131 257 VIN Main power input 9~20V
132 259 VIN Main power input 9~20V